A nano-metallic-particles-based CMOS image sensor for DNA detection

In this paper we report on a study of the CMOS image sensor detection of DNA based on self-assembled nano- metallic particles, which are selectively deposited on the surface of the passive image sensor. The nano-metallic particles effectively block the optical radiation in the visible spectrum of ordinary light source. When such a technical method is applied to DNA detection, the requirement for a special UV light source in the most popular fluorescence is eliminated. The DNA detection methodology is tested on a CMOS sensor chip fabricated using a standard 0.5 gm CMOS process. It is demonstrated that the approach is highly selective to detecting even a signal-base mismatched DNA target with an extremely-low-concentration DNA sample down to 10 pM under an ordinary light source.

A Single-Transistor Active Pixel CMOS Image Sensor Architecture

A single-transistor CMOS active pixel image sensor(1T CMOS APS)architecture is proposed,By switching the photosensing pinned diode,resetting and selecting can be achieved by diode pull-up and capacitive coupling pull-down of the source follower.Thus,the reset and selected transistors can be removed.In addition,the reset and selected signal lines can be shared to reduce the metal signal line,leading to a very high fill factor.The pixel design and operation principles are discussed in detail.The functionality of the proposed 1 T CMOS APS architecture has been experimentally verified using a fabricated chip in a standard 0.35μm CMOS AMIS technology.

An improvement to computational efficiency of the drain current model for double-gate MOSFET

As a connection between the process and the circuit design, the device model is greatly desired for emerging devices, such as the double-gate MOSFET. Time efficiency is one of the most important requirements for device modeling. In this paper, an improvement to the computational efficiency of the drain current model for double-gate MOSFETs is extended, and different calculation methods are compared and discussed. The results show that the calculation speed of the improved model is substantially enhanced. A two-dimensional device simulation is performed to verify the improved model. Furthermore, the model is implemented into the HSPICE circuit simulator in Verilog-A for practical application.

An analytic model for gate-all-around silicon nanowire tunneling field effect transistors

An analytical model of gate-all-around （GAA） silicon nanowire tunneling field effect transistors （NW-TFETs） is developted based on the surface potential solutions in the channel direction and considering the band to band tunneling （BTBT） efficiency. The three-dimensional Poisson equation is solved to obtain the surface potential distributions in the partition regions along the channel direction for the NW-TFET, and a tunneling current model using Kane＇s expression is developed. The validity of the developed model is shown by the good agreement between the model predictions and the TCAD simulation results.

A Comparative Study of Ballistic Transport Models for Nanowire MOSFETs

We comparatively study two representative ballistic transport models of nanowire metal-oxide-semiconductor field effect transistors,i.e.the Natori model and the Jiménez model.The limitations and applicability of both the models are discussed.Then the Jiménez model is extended to include atomic dispersion relations and is compared with the Natori model from the aspects of ballistic current and quantum capacitance.It is found that the Jiménez model can produce similar results compared with the more complex Natori model even at very small nanowire dimensions.

Computer Program Calculation for Distortion of Wide-Band Track and Hold Amplifier

Tow different computer calculation methods for distortion of the wide-band diode bridge track and hold amplifier (THA) are presented based on a high frequency Schottky diode model. One of the computer programs calculates the distortion of weekly nonlinear THA based on the KCL and the nonlinear-current method. The other calculates the weekly nonlinear distortion by using a Volterra series method and a nodal formulation. Comparative calculation results for the diode bridge THA have shown good agreement with these two computer program calculation methods, whereas the overall computational efficiency of the nonlinear-current method is better than that of the nodal formulation method in a special evaluation.

Design and Verification of a High Performance LED Driver with an Efficient Current Sensing Architecture

A high power buck-boost switch-mode LED driver delivering a constant 350 mA with a power efficient current sensing scheme is presented in this paper. The LED current is extracted by differentiating the output capacitor voltage and maintained by a feedback. The circuit has been fabricated in a standard 0.35 μm AMS CMOS process. Measurement results demonstrated a power-conversion efficiency over 90% with a line regulation of 8%/V for input voltage of 3.3 V and current output between 200 mA and 350 mA.

Performance improvement of solution-processed CdS/CdTe solar cells with a thin compact TiO_2 buffer layer

The device performance of CdS/CdTe solar cells largely depends on not only the back ohmic contact, but also the conformality of Cd S window layer coating. In order to reduce the light absorption loss in Cd S, the Cd S thickness is usually less than 100 nm. However, pinholes in Cd S and non-conformal coverage of Cd S on transparent conducting oxide layer will cause shunting thus leading to device performance degradation and failure. In this paper, low-temperature and low-cost fabrication methods, i.e., chemical bath deposition and electrochemical deposition, were used to deposit Cd S and Cd Te, respectively. It was found that the yield of device was around 20 % due to shunting. In order to alleviate this problem, a compact layer of TiO2 was inserted between the fluorine-doped tin oxide and Cd S as a buffer layer. The thickness effect of TiO2 was studied and showed that devices with thin(20 nm thickness) TiO2 performed better than the counterparts with thick layers. It was discovered that device yield improved to 80 % and stability in air substantially improved with TiO2 layer.

Forward gated-diode method for parameter extraction of MOSFETs

The forward gated-diode method is used to extract the dielectric oxide thickness and body doping concentration of MOSFETs, especially when both of the variables are unknown previously. First, the dielectric oxide thickness and the body doping concentration as a function of forward gated-diode peak recombination-generation （R-G） current are derived from the device physics. Then the peak R-G current characteristics of the MOSFETs with different dielectric oxide thicknesses and body doping concentrations are simulated with ISE-Dessis for parameter extraction. The results from the simulation data demonstrate excellent agreement with those extracted from the forward gated-diode method.

A SPICE model for a phase-change memory cell based on the analytical conductivity model

By way of periphery circuit design of the phase-change memory,it is necessary to present an accurate compact model of a phase-change memory cell for the circuit simulation.Compared with the present model,the model presented in this work includes an analytical conductivity model,which is deduced by means of the carrier transport theory instead of the fitting model based on the measurement.In addition,this model includes an analytical temperature model based on the 1D heat-transfer equation and the phase-transition dynamic model based on the JMA equation to simulate the phase-change process.The above models for phase-change memory are integrated by using Verilog-A language,and results show that this model is able to simulate theⅠ-Ⅴcharacteristics and the programming characteristics accurately.