Compact-Parity Testing and Testable Design

Parity testing is one of the compact testing techniques,which, traditionally, relies on applying all 2n input combinations to an n-input combinational circuit without need of knowing the implementation of the circuits under test. The faults can be detected just by observing and comparing its parity of whole output of circuit with the expectation one. The way seemed to be less interesting to the test engineers in the past days, mainly due to the reasons of its exhaustive testing and time-consuming, which became a barrier as the number of input lines gets growing. However its great facility and convenience in testing still interest to the engineers who need to have a quick look at the qualities of the circuits without generating the test patterns for a given circuit to be tested. In this paper, a new approach called pseudo-parity testing is presented to deal with the dilemma we are facing: i. e. to change an exhaustive parity testing into a non-exhaustive one, followed by a pseudoparity testable design to help realize the new way of pseudoparity testing. The idea of pseudo-parity testing presented in this paper may resume its spirits towards its promising future.

Reduction of Faults in Software Testing by Fault Domination

Although mutation testing is one of the practical ways of enhancing test effectiveness in software testing, it could be sometimes infeasible in practical work for a large scale software so that the mutation testing becomes time-consuming and even in prohibited time. Therefore, the number of faults assumed to exist in the software under test should be reduced so as to be able to confine the time complexity of test within a reasonable period of time. This paper utilizes the concept of fault dominance and equivalence, which has long been employed in hardware testing, for revealing a novel way of reducing the number of faults assumed to hide in software systems. Once the number of faults assumed in software is decreased sharply, the effectiveness of mutation testing will be greatly enhanced and become a feasible way of software testing. Examples and experimental results are presented to illustrate the effectiveness and the helpfulness of the technology proposed in the paper.

Non-Intrusive Design of Self-Checking FSM Based on Convolutional Codes

A non-intrusive design of self-checking finite state machines (FSMs) in VLSI circuits was investigated using convolutional codes. We propose a novel scheme which cannot only detect but also correct errors occurred in FSM states. The error state will be corrected and sent back to the FSM, so that the concurrent error in the current state is detected and corrected immediately. Moreover, we realize the IP core of the self-checking module by SMIC 0.25-μm CMOS technology and also simulate its function in FPGA.

A New Method for Measurement and Reduction of Software Complexity

This paper develops an improved structural software complexity metrics named information flow complexity which is closely related to the reliability of software. Together with the three software complexity metrics, the total software complexity is measured and some rules to reduce the complexity are presented in the paper. To illustrate and explain the process of measurement and reduction of software complexity, several examples and experiments are given. It is proposed that software complexity metrics can be measured earlier in software development and can provide substantial information of software systems whose reliabil- ity can be modeled and used in the determination of initial parameter estimation.