DIGITAL BACKGROUND CALIBRATION OF CAPACITOR MISMATCHES AND HARMONIC DISTORTION IN PIPELINED ADC

A correlation-based digital background calibration algorithm for pipelined Analog-to- Digital Converters (ADCs) is presented in this paper. The merit of the calibration algorithm is that the main errors information, which include the capacitor mismatches and residue amplifier distortion, are extracted integrally. A modified 1st pipelined stage is adopted to solve the signal overflow caused by the Pseudo-random Noise (PN) sequences. Behavioral simulation results verify the effectiveness of the algorithm. It improves the Signal-to-Noise-plus-Distortion Ratio (SNDR) and Spurious-Free-Dynamic-Range (SFDR) of the pipelined ADC from 41.8 dB to 78.3 dB and 55.6 dB to 98.6 dB, respectively, which is comparable to the prior arts.

Piezoresistive Characteristic of Conductive Rubber for Flexible Tactile Sensor

In the research of 2D flexible tactile sensor matrix,pressure-sensitive conductive rubber was developed and tested in which carbon black was used as its conductive phase and silicon rubber as its matrix layer.Experiments were undertaken and the resultant data were used for its piezoresistive characteristics investigation for two kinds of electrode connection configurations,the surface directive connection and embedded connection.It is found that due to the rather strong nonlinearity of the piezoresistive characteristic curves obtained,a higher correlation relationship can be obtained by means of quadratic polynomial fitting.It also showed that the embedded electrode assembling has higher fitting accuracy while the surface directive connection has better mechanical sensitivity.

A FAULT DETECTION SENSOR FOR CIRCUIT AGING USING DOUBLE-EDGE-TRIGGERED FLIP-FLOP

In nanoscale technology, transistor aging is one of the most critical problems that impact on the reliability of circuits. Aging sensor is a good online way to detect the circuit aging, which performs during the operating time with no influence of the normal operation of circuits. In this paper, a Double-edge-triggered Detection Sensor for circuit Aging (DSDA) is proposed, which employs data signal of logic circuits as its clock to control the sampling process. The simulation is done by Hspice using 45 nm technology. The results show that this technique is not sensitive to the process variations. The worst case of the detection precision is more than 80% under the different process variations. It can detect aging fault effectively with the 8% power cost and 30% performance cost.

A NOVEL LOW DISTORTION HIGH LINEARITY CMOS BOOTSTRAPPED SWITCH

This paper proposes a novel low distortion high linearity CMOS bootstrapped switch, and the proposed switch can alleviate the nonlinear distortion of the on-resistance by eliminating first order signal-dependent variation of the overdrive voltage. Based on a 0.18 mm standard CMOS process, the simulation results show that at 100 MHz sampling clock frequency and 49 MHz input signal with 2Vpp, the proposed switch in differential mode has a Spurious-Free Dynamic Range(SFDR) of 90.1 dB.

Leaf Sequencing Algorithm Based on MLC Shape Constraint

Intensity modulated radiation therapy （IMRT） requires the determination of the appropriate multileaf collimator settings to deliver an intensity map. The purpose of this work was to attempt to regulate the shape between adjacent multileaf collimator apertures by a leaf sequencing algorithm. To qualify and validate this algorithm, the integral test for the segment of the multileaf collimator of ARTS was performed with clinical intensity map experiments. By comparisons and analyses of the total number of monitor units and number of segments with benchmark results, the proposed algorithm performed well while the segment shape constraint produced segments with more compact shapes when delivering the planned intensity maps, which may help to reduce the multileaf collimator＇s specific effects.

PIPBQ Effect Aware SER Analysis for Combinational Logic Circuits

Technology scaling results in the propagation-induced pulse broadening and quenching（PIPBQ） effect become more noticeable.In order to effectively evaluate the soft error rate for combinational logic circuits,a soft error rate analysis approach considering the PIPBQ effect is proposed.As different original pulse propagating through logic gate cells,pulse broadening and quenching are measured by HSPICE.After that,electrical effect look-up tables（EELUTs） for logic gate cells are created to evaluate the PIPBQ effect.Sensitized paths are accurately retrieved by the proposed re-convergence aware sensitized path search algorithm.Further,by propagating pulses on these paths to simulate fault injection,the PIPBQ effect on these paths can be quantified by EELUTs.As a result,the soft error rate of circuits can be effectively computed by the proposed technique.Simulation results verify the soft error rate improvement comparing with the PIPBQ-not-aware method.

Covalent functionalization of graphene oxide by 9-(4-aminophenyl)acridine and its derivatives

Graphene/acridine （G-Acr） hybrid structures were synthesized through covalent functionalization of graphene oxide with 9-（4- aminophenyl）acridine （APA） and its derivatives. The G-Act hybrids were characterized by Fourier transform infrared spectroscopy, ultraviolet-visible spectrophotometry, thermal gravimetric analysis and Raman spectroscopy. X-ray photoelectron spectroscopy confirms that the binding energies of APA and its derivatives shifted to higher values, revealing pronounced charge transfer at the interface of graphene and organic molecules.

Design and comparison of new fault-tolerant majority gate based on quantum-dotcellular automata

Quantum-dot cellular automata(QCA) is increasingly valued by researchers because of its nanoscale size and very low power consumption. However, in the manufacture of nanoscale devices prone to various forms of defects, which will affect the subsequent circuits design. Therefore, fault-tolerant QCA architectures have become a new research direction. The purpose of this paper is to build a novel fault-tolerant three-input majority gate based on normal cells. Compared with the previous structures, the majority gate shows high fault tolerance under single-cell and double-cell omission defects. In order to examine the functionality of the proposed structure, some physical proofs under single cell missing defects are provided. Besides, two new fault-tolerant decoders are constructed based on the proposed majority gate. In order to fully demonstrate the performance of the proposed decoder, the previous decoders were thoroughly compared in terms of fault tolerance, area and delay. The result shows that the proposed design has a good fault tolerance characteristic, while the performance in other aspects is also quite good.

Ultraflat, broadband, and highly coherent supercontinuum generation in all-solid microstructured optical fibers with all-normal dispersion

High flatness, wide bandwidth, and high-coherence properties of supercontinuum(SC) generation in fibers are crucial in many applications. It is challenging to achieve SC spectra in a combination of the properties, since special dispersion profiles are required, especially when pump pulses with duration over 100 fs are employed. We propose an all-solid microstructured fiber composed only of hexagonal glass elements. The optimized fiber possesses an ultraflat all-normal dispersion profile, covering a wide wavelength interval of approximately 1.55 μm. An SC spectrum spanning from approximately 1030 to 2030 nm(corresponding to nearly one octave) with flatness<3 dB is numerically generated in the fiber with 200 fs pump pulses at 1.55 μm. The results indicate that the broadband ultraflat SC sources can be all-fiber and miniaturized due to commercially achievable 200-fs fiber lasers. Moreover, the SC pulses feature high coherence and a single pulse in the time domain, which can be compressed to 13.9-fs pulses with high quality even for simple linear chirp compensation. The Fourier-limited pulse duration of the spectrum is 3.19 fs, corresponding to only 0.62 optical cycles.

50 MHz dual-mode buck DC–DC converter

A 50 MHz 1.8/0.9 V dual-mode buck DC-DC converter is proposed in this paper. A dual-mode control for high-frequency DC-DC converter is presented to enhance the conversion efficiency of light-load in this paper. A novel zero-crossing detector is proposed to shut down synchronous rectification transistor NMOS when the inductor crosses zero, which can decrease the power loss caused by reverse current and the trip point is adjusted by regulating IBIAS （BIAS current）. A new logic control for pulse-skipping modulation loop is also presented in this paper, which has advantages of simple structure and low power loss. The proposed converter is realized in SMIC 0.18μm 1-poly 6-metal mixed signal CMOS process. With switching loss, conduction loss and reverse current related loss optimized, an efficiency of 57% is maintained at 10 mA, and a peak efficiency of 71% is measured at nominal operating conditions with a voltage conversion of 1.8 to 0.9 V.