Dynamic electrostatic-discharge path investigation relied on different impact energies in metal-oxide-semiconductor circuits

Gate-grounded n-channel metal-oxide-semiconductor(GGNMOS)devices have been widely implemented as power clamps to protect semiconductor devices from electrostatic discharge stress owing to their simple construction,easy triggering,and low power dissipation.We present a novel I-V characterization of the GGNMOS used as the power clamp in complementary metal-oxide-semiconductor circuits as a result of switching the ESD paths under different impact energies.This special effect could cause an unexpected latch-up or pre-failure phenomenon in some applications with relatively large capacitances from power supply to power ground,and thus should be urgently analyzed and resolved.Transmission-linepulse,human-body-modal,and light-emission tests were performed to explore the root cause.

Ambipolar performance improvement of the C-shaped pocket TFET with dual metal gate and gate–drain underlap

Dual-metal gate and gate–drain underlap designs are introduced to reduce the ambipolar current of the device based on the C-shaped pocket TFET(CSP-TFET).The effects of gate work function and gate–drain underlap length on the DC characteristics and analog/RF performance of CSP-TFET devices,such as the on-state current(I_(on)),ambipolar current(I_(amb)),transconductance(g_(m)),cut-off frequency(f_(T))and gain–bandwidth product(GBP),are analyzed and compared in this work.Also,a combination of both the dual-metal gate and gate–drain underlap designs has been proposed for the C-shaped pocket dual metal underlap TFET(CSP-DMUN-TFET),which contains a C-shaped pocket area that significantly increases the on-state current of the device;this combination design substantially reduces the ambipolar current.The results show that the CSP-DMUN-TFET demonstrates an excellent performance,including high I_(on)(9.03×10^(-4)A/μm),high I_(on)/I_(off)(~10^(11)),low SS_(avg)(~13 mV/dec),and low I_(amb)(2.15×10^(-17)A/μm).The CSP-DMUN-TFET has the capability to fully suppress ambipolar currents while maintaining high on-state currents,making it a potential replacement in the next generation of semiconductor devices.

High-performance RF Switch in 0.13 μm RF SOI process

A high-performance single-pole single-throw(SPST) RF switch for mobile phone RF front-end modules(FEMs) was designed and characterized in a 0.13 μm partially depleted silicon-on-insulator(PD SOI) process. In this paper, the traditional seriesshunt configuration design was improved by introducing a suitably large DC bias resistor and leakage-preventing PMOS, together with the floating body technique. The performance of the RF switch is greatly improved. Furthermore, a new Ron × Coff testing method is also proposed. The size of this SPST RF switch is 0.2 mm2. This switch can be widely used for present 4 G and forthcoming 5 G mobile phone FEMs.

Kinetics of leaching refractory gold ores by ultrasonic-assisted electro-chlorination

The resources of refractory gold ores are abundant, and their effective treatment can bring good economic benefits. This paper investigated the kinetics of leaching gold from refractory gold ores by ultrasonic-assisted electro-chlorination. The effects of ultrasound time ratio, initial hydrochloric acid concentration and leaching temperature on the kinetic parameters were discussed. It is found that the leaching ratio goes up with all the factors increasing. The reaction kinetics is controlled by diffusion. When ultrasound improves the diffusion by reducing the diffusion resistance, the activation energy increases to 37.1 kJ/mol.

A Phase Change Memory Chip Based on Ti Sb Te Alloy in 40-nm Standard CMOS Technology

In this letter, a phase change random access memory(PCRAM) chip based on Ti0.4Sb2Te3 alloy material was fabricated in a 40-nm 4-metal level complementary metal-oxide semiconductor(CMOS) technology. The phase change resistor was then integrated after CMOS logic fabrication. The PCRAM was successfully embedded without changing any logic device and process, in which 1.1 V negative-channel metal-oxide semiconductor device was used as the memory cell selector. The currents and the time of SET and RESET operations were found to be 0.2 and 0.5 m A, 100 and 10 ns,respectively. The high speed performance of this chip may highlight the design advantages in many embedded applications.

Extraction and stripping kinetics of copper(Ⅱ)by N902 using single drop technique

The kinetics of extraction and stripping of copper （Ⅱ） was investigated by the single drop technique with a new extractant N902 （a derivative of the salicylal-doxime） and the rate equations of extraction and stripping were derived, respectively. The apparent activation energies of extraction and stripping were estimated to be 20.14 kJ/mol and 30.0 k J/mol.

Nano-scale gap filling and mechanism of deposit-etch-deposit process for phase-change material

Ge2Sb2Te5 gap filling is one of the key processes for phase-change random access memory manufacture. Physical vapor deposition is the mainstream method of Ge2Sb2Te5 film deposition due to its advantages of film quality, purity, and accurate composition control. However,the conventional physical vapor deposition process cannot meet the gap- filling requirement with the critical device dimension scaling down to 90 nm or below. In this study, we find that the deposit-etch-deposit process shows better gap-filling capability and scalability than the single-step deposition process, especially at the nano-scale critical dimension. The gap-filling mechanism of the deposit-etch-deposit process was briefly discussed. We also find that re-deposition of phase-change material from via the sidewall to via the bottom by argon ion bombardment during the etch step was a key ingredient for the final good gap filling. We achieve void-free gap filling of phase-change material on the 45-nm via the two-cycle deposit-etch-deposit process. We gain a rather comprehensive insight into the mechanism of deposit-etch-deposit process and propose a potential gap-filling solution for over 45-nm technology nodes for phase-change random access memory.

Chemical mechanical planarization of Ge_2Sb_2Te_5 using IC1010 and Politex reg pads in acidic slurry

In the paper, chemical mechanical planarization （CMP） of Ge2 Sb2Te5 （GST） is investigated using IC 1010 and Politex reg pads in acidic slurry. For the CMP with blank wafer, it is found that the removal rate （RR） of GST increases with the increase of pressure for both pads, but the RR of GST polished using IC 1010 is far more than that of Politex reg. To check the surface defects, GST film is observed with an optical microscope （OM） and scanning electron microscope （SEM）. For the CMP with Politex reg, many spots are observed on the surface of the blank wafer with OM, but no obvious spots are observed with SEM. With regard to the patterned wafer, a few stains are observed on the GST cell, but many residues are found on other area with OM. However, from SEM results, a few residues are observed on the GST cell, more dielectric loss is revealed about the trench structure. For the CMP with IC1010, the surface of the polished blank wafer suffers serious scratches found with both OM and SEM, which may result from a low hardness of GST, compared with those of IC1010 and abrasives. With regard to the patterned wafer, it can achieve a clean surface and almost no scratches are observed with OM, which may result from the high-hardness SiO2 film on the surface, not from the soft GST film across the whole wafer. From the SEM results, a clean interface and no residues are observed on the GST surface, and less dielectric loss is revealed. Compared with Politex reg, the patterned wafer can achieve a good performance after CMP using IC1010.

45到32纳米:又一次渐进式的转变

闪存的等比例缩小很快就将遇到物理壁垒。目前正在研究的替代方案包括基于氮化物的结构、相变存储器、铁电RAM、磁性RAM和新的电阻翻转存储结构。

纳米压印技术:32纳米光刻之选?

设想一下,如果能够一步实现低介电常数绝缘材料的双大马士革结构(包括通孔和金属导线槽),就能减少123步的工艺步骤。这就是纳米压印技术所能够带来的惊人之处。此外,这项技术成本低廉、潜力无限。

高折射率镜头推动浸没式光刻跨越32纳米

在今年的SPIE Microlithography年会上，与会的专家们一如既往地针对如何延伸光学光刻技术使用寿命的问题进行了大量的研讨。而与往年会议不同的是，尽管有人心存疑虑，但今年的会议仍然对双重曝光技术打开了友善之门。关于这项技术，普遍的问题是如何妥善地解决图形套准的问题，对于逻辑电路芯片的生产工艺而言，由于其没有大量的密集线条，因此也就能够较好地归避上述的风险。

先进光刻技术大步向前

正如半导体国际杂志上所说的那样，在今年的SPIE Microlithography会议上，光刻领域的技术专家们共聚一堂并发表了他们的最新研究成果。毫无疑问本次会议将会产生更多的新闻和技术热点，而近来公布的一些关于前沿浸没式光刻技术和极紫外光刻技术（EUV）的新闻以及研究成果已经受到了广泛的关注和极大的重视。

清除浸没式光刻缺陷

来自台积电（TSMC）的工程师们已经找到通过比较光学显微镜图像和扫描电子显微镜（SEM）图像来跟踪缺陷来源的方法，从而成功地将浸没式曝光的300mm硅片上的平均缺陷数目从19.7减少到4．8个微粒／硅片。包括TSMC的Lin-Hung Shiu和Fu-Jye Liang等研究人员，在二月份召开的SPIE先进光刻技术（Advanced Lithography）会议上报告了他们减少浸没式光刻缺陷的方法。该方法涉及到缺陷数据库的建立和新型曝光程序的采用，以降低整体缺陷率并提高成品率。

Cu/低k对45和32nm节点的挑战

半导体产业正处于限制等比例缩小的基本物理规则开始挑战铜互连技术可扩展性的非常时期。它们包括表面界面所引起的电迁移，基于电子波长与互连尺寸相对大小的电子散射，以及介质常数、电学特性和机械强度等方面的物理极限。这些是Semiconductor Intemationa]最近主办的webcast所得出的主要结论，Dan Edelstein（IBM）、Rudi Cartuyvels（IMEC）、Sitaram Arkalgud（Sematech）．Gurtej Sandhu（Micron）和Jim Ryan（Albany NanoTech）等几位专家参与讨论了互连对未来逻辑和存储器件的挑战。

基于SiC材料的BJT作为高效功率器件的复兴

SiC BJT代表了最具吸引力的SiC开关结构之一,具有很低的电阻系数、较快的开关速度以及较小的温度依赖性。其良好的短路能力及不存在二次击穿可实现器件可靠工作。我们对与实际应用直接相关的器件性能进行了详细研究,并对以降耗为目的的驱动解决方案进行了测试。鉴于光伏系统降低成本的压力不断增加,我们额外进行了以实现节约为目的的实验,不仅基于SiC技术,同时包括新型磁芯材料方面。为此,我们在实验室中对一个额定功率为17kW的小型升压转换器进行了测试,并在本文中给出了结果。

缺陷问题驱动浸没光刻技术发展

虽然现在推测浸没光刻技术的量产时间还太早，但是许多公司正在努力确定生产线何时能从干法工艺跃为湿法工艺。根据最近在San Jose举办的SPIE Microlithography会议的迹象来看，工程师们正在迅速克服开发和生产之间存在的各种难题。在展览中，TSMC宣布它已采用浸没光刻技术制作了测试晶圆，每个300mm晶圆上无论何处都只有三到七个缺陷．可与干法193nm光刻技术相媲美。TSMC人说他们正用所拥有的缺陷减少专利技术达到此水平。在SPIE专题报告中，IMEC的Kurt Ronse表达了浸没光刻技术不久将用于生产的信心。同时他补充：“浸没光刻技术用于生产后，缺陷问题的解决将指日可待。”

晶圆清洗与表面预处理:从演变到革新

随着器件尺寸的不断缩小和规范的日趋严格,清洗所面临的大多数挑战都处于不断地演变发展之中。各种新材料、新集成方案和新工艺流程的引入,正在带来一场清洗的革命。

日本制造商公布存储器/晶体管技术

几家日本公司在6月12-16日于日本Kyoto举行的2007年VLSI技术与电路研讨会上，发布了多项重大技术进展：Toshiba公布一种在现有工艺基础上提高芯片密度的3-D单元阵列技求Fujitsu宣布推出一种新型的低功耗／高性能45nm平台，而Renesas Technology则首次展示一种用于微处理器和片上系统（SoC）的低成本高性能晶体管技术。

碳纳米管:诱人的互连替代方案

碳纳米管（CNT）将在未来的片上互连制造中扮演重要的角色。CNT具有许多独特的性能，包括负载超过109A／cm^2的高密度电流的能力，这比常规导线约高三个数量级；超高的热传导率，电子能够沿着碳纳米管进行弹道式输运；以及非常好的机械强度，而且还不会发生电迁移（EM）。

高k和金属栅——45nm的起点

在被称作“40年来电脑芯片的最大变化“的新闻发布中．Intel宣布将45nm节点的生产中引入铪基（hafnium—based）高k栅电介质和金属栅电极。在Intet之后，IBM也很快发布一个类似的通告。高k栅电介质在两个方面优于现在使用的氮氧化硅较小的栅泄漏电流和较大的驱动电流。它还可以使未来的器件能够进一步地等比例缩小，因为常规的电介质已经相当薄．厚度只有约5个原子。据估计，几乎一半的芯片功耗是由穿透薄层电介质的泄漏电流所引起的。