DFM:“Design for Manufacturing”or“Design Friendly Manufacturing”

As the IC manufacturing enter sub 20nm tech nodes,DFM become more and more important to make sure more stable yield and lower cost.However,by introducing newly designed hardware(1980i etc.)process chemical(NTD)and Control Algorithm(Focus APC)into the mature tech nodes such as 14nm/12nm,more process window and less process variations are expected for latecomer wafer fabs(Tier-2/3 companies)who just started the competition with Tier-1 companies.With improved weapons,latecomer companies are able to review their DFM strategy one more time to see whether the benefit from hardware/process/control algorithm improvement can be shared with designers.In this paper,we use OPC simulation tools from different EDA suppliers to see the feasibility of transferring the benefits of hardware/process/control algorithm improvement to more relaxed design limitation through source mask optimization(SMO):1)Better hardware:scanner(better focus/exposure variation),CMP(intrafield topo),Mask CD variation(relaxed MEEF spec),etc.2) New process:from positive tone development to negative tone development.3)Better control schemes:holistic focus feedback,feedback/forward overlay control,high order CD uniformity improvement.Simulations show all those gains in hardware and process can be transferred into more relaxed design such as sub design rule structure process window include forbidden pitches(1D)and smaller E2E gaps(2D weak points).

A Device Design for 5 nm Logic FinFET Technology

With the continuous scaling in conventional CMOS technologies,the planar MOSFET device is limited by the severe short-channel-effect(SCE),Multi-gate FETs(MuG-FET)such as FinFETs and Nanowire,Nanosheet devices have emerged as the most promising candidates to extend the CMOS scaling beyond sub-22 nm node.The multi-gate structure has better short channel behaviors due to enhanced control from the multiple gates.Due to the relatively more mature process and rich learning of the device physics,the FinFET is still extended to 5 nm technology node.In this paper,we proposed a 5 nm FINFET device,which is based on typical 5 nm logic design rules.To achieve the challenging device performance target,which is around 15%speed gain or 25%power reduction against the 7 nm device,we have performed an optimization on the process parameters and iterate through device simulation with the consideration of current process capability.Based on our preferred device architecture,we provide our brief process flow,key dimensions,and simulated device DC/AC performance,like Vt,Idsat,SS,DIBL and parasitic parameters.As a part of the final evaluation,RO simulation result has been checked,which demonstrates that the Performance Per Area(PPA)is close to industry reference 5 nm performance.

A 0.23 pJ 11.05-bit ENOB 125-MS/s pipelined ADC in a 0.18 μm CMOS process

This paper describes a 12-bit 125-MS/spipelinedanalog-to-digitalconverter（ADC）thatisimplemented in a 0.18 #m CMOS process. A gate-bootstrapping switch is used as the bottom-sampling switch in the first stage to enhance the sampling linearity. The measured differential and integral nonlinearities of the prototype are less than 0.79 least significant bit （LSB） and 0.86 LSB, respectively, at the full sampling rate. The ADC exhibits an effective number of bits （ENOB） of more than 11.05 bits at the input frequency of 10.5 MHz. The ADC also achieves a 10.5 bits ENOB with the Nyquist input frequency at the full sample rate. In addition, the ADC consumes 62 mW from a 1.9 V power supply and occupies 1.17 mm2, which includes an on-chip reference buffer. The figure-of-merit of this ADC is 0.23 p J/step.

An improved HCI degradation model for a VLSI MOSFET

An improved hot carrier injection （HCI） degradation model was proposed based on interface trap generation and oxide charge injection theory. It was evident that the degradation behavior of electric parameters such as Idlin, Idsat, Gm and Vt fitted well with this model. Devices were prepared with 0.35μm technology and different LDD processes. Idlin and Idsat after HCI stress were analyzed with the improved model. The effects of interface trap generation and oxide charge injection on device degradation were extracted, and the charge injection site could be obtained by this method. The work provides important information to device designers and process engineers.