A novel P-channel SOI LDMOS structure with non-depletion potential-clamped layer

A novel structure is proposed for doubling the vertical breakdown voltage of silicon-on-insulator(SOI) devices. In this new structure, the conventional buried oxide(BOX) in an SOI device is split into two sections: the source-section BOX and the drain-section BOX. A highly-doped Si layer, referred to as a non-depletion potential-clamped layer(NPCL), is positioned under and close to the two BOX sections. In the split BOXes and the Si region above the BOXes, the blocking voltage(BV) is divided into two parts by the NPCL. The voltage in the NPCL is clamped to be nearly half of the drain voltage. When the drain voltage approaches a breakdown value, the voltage sustained by the source-section BOX and the Si region under the source are nearly the same as the voltage sustained by the drain-section BOX and the Si region under the drain. The vertical BV is therefore almost doubled. The effectiveness of this new structure was verified for a P-channel SOI lateral double-diffused metal-oxide semiconductor(LDMOS) and can be applied to other high-voltage SOI devices. The simulation results show that the BV in an NPCL P-channel SOI LDMOS is improved by 55% and the specific on-resistance(Ron,sp) is reduced by 69% in comparison to the conventional structure.

Numerical and Experimental Investigations of the Thermal Fatigue Lifetime of CBGA Packages

A thermal fatigue lifetime prediction model of ceramic ball grid array(CBGA)packages is proposed based on the Darveaux model.A finite element model of the CBGA packages is established,and the Anand model is used to describe the viscoplasticity of the CBGA solder.The average viscoplastic strain energy density increment △Wave of the CBGA packages is obtained using a finite element simulation,and the influence of different structural parameters on theWave is analyzed.A simplified analytical model of the △Wave is established using the simulation data.The thermal fatigue lifetime of CBGA packages is obtained from a thermal cycling test.The Darveaux lifetime predictionmodel ismodified based on the thermal fatigue lifetime obtained fromthe experiment and the corresponding △Wave.A validation test is conducted to verify the accuracy of the thermal fatigue lifetime prediction model of the CBGA packages.This proposed model can be used in engineering to evaluate the lifetime of CBGA packages.

Breakdown voltage enhancement in GaN channel and AlGaN channel HEMTs using large gate metal height

A large gate metal height technique is proposed to enhance breakdown voltage in GaN channel and AlGaN channel high-electron-mobility-transistors(HEMTs).For GaN channel HEMTs with gate-drain spacing LGD=2.5μm,the breakdown voltage VBR increases from 518 V to 582 V by increasing gate metal height h from 0.2μm to 0.4μm.For GaN channel HEMTs with LGD=7μm,VBR increases from 953 V to 1310 V by increasing h from 0.8μm to 1.6μm.The breakdown voltage enhancement results from the increase of the gate sidewall capacitance and depletion region extension.For Al0.4Ga0.6N channel HEMT with LGD=7μm,VBR increases from 1535 V to 1763 V by increasing h from 0.8μm to 1.6μm,resulting in a high average breakdown electric field of 2.51 MV/cm.Simulation and analysis indicate that the high gate metal height is an effective method to enhance breakdown voltage in GaN-based HEMTs,and this method can be utilized in all the lateral semiconductor devices.

Silicon-on-Insulator 2×2 Symmetric Optical Switch Based on Total Internal Reflection

Based on the large cross-section single-mode rib waveguide condition,the total internal reflection and the free-carrier plasma dispersion effect,a silicon-on-insulator(SOI)2×2 symmetric optical waveguide switch with a transverse injection structure has been proposed and fabricated,in which the SOI technique utilizes silicon and silicon dioxide thermal bonding and back-polishing.The device performance is measured at the wavelength of 1.3μm.It shows that the crosstalk and insertion loss are less than -18.1 and 4.8 dB,respectively,at an injection current of 60mA,and response time is 110 ns.

Design of a 1200-V Thin-Silicon-Layer p-Channel SOI LDMOS Device

A 1200-V thin-silicon-layer p-channel silicon-on-insulator(SOI)lateral double-diffused metal-oxide-semiconductor(LDMOS)transistor is designed.The device named INI SOI p-LDMOS is characterized by a series of equidistant high concentration n+islands inserted at the interface of a top silicon layer and a buried oxide layer.Accumulation−mode holes,caused by the electric potential dispersion between the device surface and the substrate,are located in the spacing between two neighboring n+islands,and greatly enhance the electric field of the buried oxide layer and therefore,effectively increase the device breakdown voltage.Based on a 2−µm−thick buried oxide layer and a 1.5-µm−thick top silicon layer,a breakdown voltage of 1224 V is obtained,resulting in the high electric field(608 V/µm)of the buried oxide layer.

A Matlab/Simulink Development and Verification Platform for a Frequency Estimation System

The precise estimation of the frequency of the signal is of great significance in the Radar system, the electronic warfare system and many other systems. In this paper, we propose a development and verification platform for the frequency estimation system in the Matlab and Simulink environment. Its open-extensibility architecture enables the performance evaluation of different frequency estimation algorithms and its graphic interface can greatly promote the system design, simulation and verification efficiency.

A novel structure in reducing the on-resistance of a VDMOS

A novel structure of a VDMOS in reducing on-resistance is proposed.With this structure,the specific on-resistance value of the VDMOS is reduced by 22%of that of the traditional VDMOS structure as the breakdown voltage maintained the same value in theory,and there is only one additional mask in processing the new structure VDMOS,which is easily fabricated.With the TCAD tool,one 200 V N-channel VDMOS with the new structure is analyzed,and simulated results show that a specific on-resistance value will reduce by 23%,and the value by 33% will be realized when the device is fabricated in three epitaxies and four buried layers.The novel structure can be widely used in the strip-gate VDMOS area.

A 150%enhancement of PMOSFET mobility using hybrid orientation

A high-performance PMOSFET based on silicon material of hybrid orientation is obtained.Hybrid orientation wafers,integrated by（100） and（110） crystal orientation,are fabricated using silicon-silicon bonding, chemical mechanical polishing,etching silicon and non-selective expitaxy.A PMOSFET with W/L = 50μm/8μm is also processed,and the measured results show that the drain-source current and peak mobility of the PMOSFET are enhanced by up to 50.7%and 150%at Vgs =-15 V and Vds =-0.5 V,respectively.The mobility values are higher than that reported in the literature.

A novel structure for improving the SEGR of a VDMOS

The mechanism of single-event gate-rupture in an N-channel VDMOS in a space radiation environment was analyzed.Based on the mechanism,a novel structure of VDMOS for improving single-event gate-rupture is proposed,and the structure is simulated and it is demonstrated that it can improve a VDMOS SEGR threshold voltage by 120%.With this structure,the specific on-resistance value of a VDMOS is reduced by 15.5%as the breakdown voltage almost maintains the same value.As only one mask added,which is local oxidation of silicon instead of an active processing area,the new structure VDMOS it is easily fabricated.The novel structure can be widely used in high-voltage VDMOS in a space radiation environment.

Study of hybrid orientation structure wafer

Two types of 5μm thick hybrid orientation structure wafers,which were integrated by（110）or（100） orientation silicon wafers as the substrate,have been investigated for 15-40 V voltage ICs and MEMS sensor applications.They have been obtained mainly by SOI wafer bonding and a non-selective epitaxy technique,and have been presented in China for the first time.The thickness of BOX SiO2 buried in wafer is 220 nm.It has been found that the quality of hybrid orientation structure with（100）wafer substrate is better than that with（110）wafer substrate by'Sirtl defect etching of HOSW'.

Design and application of a depletion-mode NJFET in a high-voltage BiCMOS process

A novel depletion-mode NJFET compatible high-voltage BiCMOS process is proposed and experimentally demonstrated with a four-branch 12-bit DAC(digital-to-analog converter).With this process,an NJFET with a pinch-off voltage ofabout-1.5 V and a breakdown voltage of about 16 V,an NLDDMOS(N-type lightly-dosed-drain in MOS) with a turn-on voltage of about 1.0 V and a breakdown voltage of about 35 V,and a Zener diode with a reverse voltage of about 5.6 V were obtained.Measurement results showed that the converter had a reference temperature coefficient of less than±25 ppm/℃,a differential coefficient error of less than±0.3 LSB,and a linear error of less than±0.5 LSB.The depletion-mode NJFET and its compatible process can also be widely used for high-voltage ADCs or DACs.

Design of a high-performance PJFET for the input stage of an integrated operational amplifier

With Shockley's approximate-channel theory and TCAD tools,a high-voltage,ultra-shallow junction PJFET for the input stage of an integrated operational amplifier(OPA) was realized.The high-performance PJFET device was developed in the Bi-FET process technology.The measured specifications are as follows.The top-gate junction depth is about 0.1μm,the gate-leakage current is less than 5 pA,the breakdown voltage is more than 80 V, and the pinch-offvoltage is optional between 0.8 and 2.0 V.The device and its Bi-FET process technology were used to design and process a high input-impedance integrated OPA.The measured results show that the OPA has a bias current of less than 50 pA,voltage noise of less than 50 nV/Hz^(1/2),and current noise of less than 0.05 pA/Hz^(1/2).

A novel terminal structure for total dose irradiation hardened of a P-VDMOS

Using positive surface charge instead of traditional-ray total dose irradiation, the electric field distribution of a P-channel VDMOS terminal has been analyzed. A novel terminal structure for improving the total dose irradiation hardened of P-channel VDMOS has been proposed,and the structure is simulated and demonstrated with a –150 V P-channel VDMOS. The results show that the peak current density is reduced from 5.51 103A/cm2to 2.01 103A/cm2, and the changed value of the breakdown voltage is 2.5 V at 500 krad(Si). Especially, using 60 Co and X-ray to validate the results, which strictly match with the simulated values, there is not any added mask or process to fabricate the novel structure, of which the process is compatible with common P-channel VDMOS processes. The novel terminal structure can be widely used in total irradiation hardened P-channel VDMOS design and fabrication, which holds a great potential application in the space irradiation environment.

A 10-bit 110 MHz SAR ADC with asynchronous trimming in 65-nm CMOS

A 10-bit 110 MHz SAR ADC with asynchronous trimming is presented.In this paper,a high linearity sampling switch is used to produce a constant parasitical barrier capacitance which would not change with the range of input signals.As a result,the linearity of the SAR ADC will increase with high linearity sampled signals.Farther more,a high-speed and low-power dynamic comparator is proposed which would reduce the comparison time and save power consumption at the same time compared to existing technology.Additionally,the proposed comparator provides a better performance with the decreasing of power supply.Moreover,a highspeed successive approximation register is exhibited to speed up the conversion time and will reduce about 50%register delay.Lastly,an asynchronous trimming method is provided to make the capacitive-D AC settle up completely instead of using the redundant cycle which would prolong the whole conversion period.This SAR ADC is implemented in 65-nm CMOS technology the core occupies an active area of only 0.025 mm^2 and consumes 1.8 mW.The SAR ADC achieves SFDR > 68 dB and SNDR > 57 dB,resulting in the FOM of 28 f J/conversion-step.From the test results,the presented SAR ADC provides a better FOM compared to previous research and is suitable for a kind of ADC IP in the design SOC.