Impact of low-dose radiation on nitrided lateral 4H-SiC MOSFETs and the related mechanisms

Lateral type n-channel 4H-SiC metal–oxide–semiconductor field effect transistors(MOSFETs),fabricated using a current industrial process,are irradiated with gamma rays at different irradiation doses in this paper to carry out a profound study on the generation mechanism of radiation-induced interface traps and oxide trapped charges.Electrical parameters(e.g.,threshold voltage,subthreshold swing and channel mobility)of the device before and after irradiation are investigated,and the influence of the channel orientation([1100]and[1120])on the radiation effect is discussed for the first time.A positive threshold voltage shift is observed at very low irradiation doses(<100 krad(Si));the threshold voltage then shifts negatively as the dose increases.It is found that the dependence of interface trap generation on the radiation dose is not the same for doses below and above 100 krad.For irradiation doses<100 krad,the radiation-induced interface traps with relatively high generation speeds dominate the competition with radiation-induced oxide trapped charges,contributing to the positive threshold voltage shift correspondingly.All these results provide additional insight into the radiation-induced charge trapping mechanism in the SiO_(2)/SiC interface.

Characteristics and mechanisms of subthreshold voltage hysteresis in 4H-SiC MOSFETs

In order to investigate the characteristics and mechanisms of subthreshold voltage hysteresis(ΔV_(th,sub)) of 4 H-SiC metal-oxide-semiconductor field-effect transistors(MOSFETs),4 H-SiC planar and trench MOSFETs and corresponding P-type planar and trench metal-oxide-semiconductor(MOS) capacitors are fabricated and characterized.Compared with planar MOSFEF,the trench MOSFET shows hardly larger ΔV_(th,sub) in wide temperature range from 25 0 C to 300 0 C.When operating temperature range is from 25 ℃ to 300 ℃,the off-state negative V_(gs) of planar and trench MOSFETs should be safely above-4 V and-2 V,respectively,to alleviate the effect of ΔV_(th,sub) on the normal operation.With the help of P-type planar and trench MOS capacitors,it is confirmed that the obvious ΔV_(th,sub) of 4 H-SiC MOSFET originates from the high density of the hole interface traps between intrinsic Fermi energy level(E_(i)) and valence band(E_(v)).The maximumΔV_(th,sub) of trench MOSFET is about twelve times larger than that of planar MOSFET,owing to higher density of interface states(D_(it)) between E_(i) and E_(v).These research results will be very helpful for the application of 4 H-SiC MOSFET and the improvement of ΔV_(th,sub) of 4 H-SiC MOSFET,especially in 4 H-SiC trench MOSFET.