Effect of Temperature &Supply Voltage Variation on Stability of 9T SRAM Cell at 45 nm Technology for Various Process Corners

Due to the continuous rising demand of handheld devices like iPods, mobile, tablets;specific applications like biomedical applications like pacemakers, hearing aid machines and space applications which require stable digital systems with low power consumptions are required. As a main part in digital system the SRAM (Static Random Access Memory) should have low power consumption and stability. As we are continuously moving towards scaling for the last two decades the effect of this is process variations which have severe effect on stability, performance. Reducing the supply voltage to sub-threshold region, which helps in reducing the power consumption to an extent but side by side it raises the issue of the stability of the memory. Static Noise Margin of SRAM cell enforces great challenges to the sub threshold SRAM design. In this paper we have analyzed the cell stability of 9T SRAM Cell at various processes. The cell stability is checked at deep submicron (DSM) technology. In this paper we have analyzed the effect of temperature and supply voltage (Vdd) on the stability parameters of SRAM which is Static Noise Margin (SNM), Write Margin (WM) and Read Current. The effect has been observed at various process corners at 45 nm technology. The temperature has a significant effect on stability along with the Vdd. The Cell has been working efficiently at all process corners and has 50% more SNM from conventional 6T SRAM and 30% more WM from conventional 6T SRAM cell.

Group delay and phase delay in GNSS systems

GNSS signals have previously been modulated using binary phase shift keying but this modulation scheme is being replaced by binary offset carrier(BOC)modulation.Research has considered how the BOC signals might be affected differently when passed through a surface acoustic wave(SAW)filter.The concern has been that because of the split spectrum nature of the BOC signals,the upper and lower side-lobes will be delayed significantly differently.This was suggested because SAW filters have nonlinear phase characteristics and therefore different frequencies are delayed differently.It was suggested that this difference in delay will result in greater distortion of the correlation triangle.A delay magnification effect was also mentioned when analyzing the delay of a BOC signal.It was not understood why the theoretical delay calculations did not match up with the actual results in both hardware and simulation.This paper clarifies some of the confusion and explains why the“delay magnification”applies to phase delay but not group delay.This paper also takes a look at how the code phase delay can vary with frequency and correlator spacing as a result of the SAW filter properties.

Modeling and simulation of enhancement mode p-GaN Gate AlGaN/GaN HEMT for RF circuit switch applications

An enhancement mode p-GaN gate AlGaN/GaN HEMT is proposed and a physics based virtual source charge model with Landauer approach for electron transport has been developed using Verilog-A and simulated using Cadence Spectre,in order to predict device characteristics such as threshold voltage,drain current and gate capacitance.The drain current model incorporates important physical effects such as velocity saturation,short channel effects like DIBL（drain induced barrier lowering）,channel length modulation（CLM）,and mobility degradation due to self-heating.The predicted Id–V（ds）,Id–V（gs）,and C–V characteristics show an excellent agreement with the experimental data for both drain current and capacitance which validate the model.The developed model was then utilized to design and simulate a single-pole single-throw（SPST）RF switch.

Small-signal model parameter extraction of E-mode N-polar GaN MOS-HEMT using optimization algorithms and its comparison

An improved small-signal parameter extraction technique for short channel enhancement-mode N-polar GaN MOS-HEMT is proposed, which is a combination of a conventional analytical method and optimization techniques. The extrinsic parameters such as parasitic capacitance, inductance and resistance are extracted under the pinch-off condition. The intrinsic parameters of the small-signal equivalent circuit（SSEC） have been extracted including gate forward and backward conductance. Different optimization algorithms such as PSO, Quasi Newton and Firefly optimization algorithm is applied to the extracted parameters to minimize the error between modeled and measured S-parameters. The different optimized SSEC models have been validated by comparing the S-parameters and unity current-gain with TCAD simulations and available experimental data from the literature. It is observed that the Firefly algorithm based optimization approach accurately extracts the small-signal model parameters as compared to other optimization algorithm techniques with a minimum error percentage of 1.3%.

Modeling on oxide dependent 2DEG sheet charge density and threshold voltage in AlGaN/GaN MOSHEMT

We have developed a physics based analytical model for the calculation of threshold voltage, two dimensional electron gas（2DEG） density and surface potential for Al Ga N/Ga N metal oxide semiconductor high electron mobility transistors（MOSHEMT）. The developed model includes important parameters like polarization charge density at oxide/Al Ga N and Al Ga N/Ga N interfaces, interfacial defect oxide charges and donor charges at the surface of the Al Ga N barrier. The effects of two different gate oxides（Al_2O_3 and HfO_2/ are compared for the performance evaluation of the proposed MOSHEMT. The MOSHEMTs with Al_2O_3 dielectric have an advantage of significant increase in 2DEG up to 1.2 10^（13） cm^2 with an increase in oxide thickness up to 10 nm as compared to HfO_2 dielectric MOSHEMT. The surface potential for HfO_2 based device decreases from 2 to –1.6 e V within10 nm of oxide thickness whereas for the Al_2O_3 based device a sharp transition of surface potential occurs from 2.8to –8.3 e V. The variation in oxide thickness and gate metal work function of the proposed MOSHEMT shifts the threshold voltage from negative to positive realizing the enhanced mode operation. Further to validate the model,the device is simulated in Silvaco Technology Computer Aided Design（TCAD） showing good agreement with the proposed model results. The accuracy of the developed calculations of the proposed model can be used to develop a complete physics based 2DEG sheet charge density and threshold voltage model for Ga N MOSHEMT devices for performance analysis.

Performance analysis of a complete adiabatic logic system driven by the proposed power clock generator

We analyze the energy performance of a complete adiabatic circuit/system including the Power Clock Generator （PCG） at the 90 nm CMOS technology node. The energy performance in terms of the conversion efficiency of the PCG is extensively carried out under the variations of supply voltage, process comer and the driver transistor＇s width. We propose an energy-efficient singe cycle control circuit based on the two-stage comparator for the synchronous charge recovery sinusoidal power clock generator （PCG）. The proposed PCG is used to drive the 4-bit adiabatic Ripple Carry Adder （RCA） and their simulation results are compared with the adiabatic RCA driven by the reported PCG. We have also simulated the logically equivalent static CMOS RCA circuit to compare the energy saving of adiabatic and non-adiabatic logic circuits. In the clock frequency range from 25 MHz to 1GHz, the proposed PCG gives a maximum conversion efficiency of 56.48%. This research work shows how the design of an efficient PCG increases the energy saving of adiabatic logic.

Effect of metal-fingers/doped-ZnO transparent electrode on performance of GaN/InGaN solar cell

The effect of doped-ZnO transparent conductive oxide （TCO） with metal （Ag）-fingers contact on GaN/InGaN solar cell is investigated through numerical simulations. An optical and electrical analysis of different dopant elements （such as B, A1, Ga, In and Sn） with ZnO as a top TCO layer is studied. A comparative analysis of metal square pad electrode, metal grid pattern electrode and metal-finger/ZnO type electrodes are taken into consideration to ensure the effect of anti-reflectivity by ZnO. The effect of thickness of ZnO and i-InGaN layer on performance of solar cell is also studied in detail. The proposed solar cell structure with Ag-fingers/ZnO：Al as top contact electrode shows interesting device characteristics compared to other dopants and metal top electrodes. The device achieves open circuit voltage -2.525 V, short circuit current -4.256 mA/cm^2, fill factor -87.86% and efficiency -9.22% under 1 Sun, air mass 1.5 global illumination.

A transformed analytical model for thermal noise of FinFET based on fringing field approximation

This paper delineates the effect of nonplanar structure of Fin FETs on noise performance. We demonstrate the thermal noise analytical model that has been inferred by taking into account the presence of an additional inverted region in the extended（underlap） S/D region due to finite gate electrode thickness. Noise investigation includes the effects of source drain resistances which become significant as channel length becomes shorter. In this paper, we evaluate the additional noise caused by three dimensional（3-D） structure of the single fin device and then extended analysis of the multi-fin and multi-fingers structure. The addition of fringe field increases its minimum noise figure and noise resistance of approximately 1 d B and 100Ω respectively and optimum admittance increases to 5.45 mΩ at 20 GHz for a device operating under saturation region. Hence, our transformed model plays a significant function in evaluation of accurate noise performance at circuit level.

Scaling trends in energy recovery logic:an analytical approach

This paper presents an analytical model to study the scaling trends in energy recovery logic.The energy performance of conventional CMOS and energy recovery logic are compared with scaling the design and technology parameters such as supply voltage,device threshold voltage and gate oxide thickness.The proposed analytical model is validated with simulation results at 90 nm and 65 nm CMOS technology nodes and predicts the scaling behavior accurately that help us to design an energy-efficient CMOS digital circuit design at the nanoscale.This research work shows the adiabatic switching as an ultra-low-power circuit technique for sub-100 nm digital CMOS circuit applications.

Analysis of morphological,structural and electrical properties of annealed TiO2 nanowires deposited by GLAD technique

The effect of annealing on vertically aligned TiO2 NWs deposited by glancing angle deposition（GLAD）method on Si substrate using pressed and sintered TiO2 pellets as source material is studied.The FE-SEM images reveal the retention of vertically aligned NWs on Si substrate after annealing process.The EDS analysis of TiO2NWs sample annealed at 600 ℃ in air for 1 h shows the higher weight percentage ratio of ～2.6（i.e.,72.27%oxygen and 27.73%titanium）.The XRD pattern reveals that the polycrystalline nature of anatase TiO2 dominates the annealed NWs sample.The electrical characteristics of Al/TiO2-NWs/TiO2-TF/p-Si（NW device） and Al/TiO2-TF/p-Si（TF device） based on annealed samples are compared.It is riveting to observe a lower leakage current of ～1.32 × 10^-7 A/cm^2 at ＋1 V with interface trap density of-6.71 × 10^11eV^-1cm^-2 in NW device compared to ～2.23 × 10^-2 A/cm^2 in TF device.The dominant leakage mechanism is investigated to be generally Schottky emission;however Poole-Frenkel emission also takes place during high reverse bias beyond 4 V for NWs and 3 V for TF device.

Gate leakage current reduction in IP3 SRAM cells at 45 nm CMOS technology for multimedia applications

We have presented an analysis of the gate leakage current of the IP3 static random access memory （SRAM） cell structure when the cell is in idle mode（performs no data read/write operations） and active mode （performs data read/write operations）,along with the requirements for the overall standby leakage power,active write and read powers.A comparison has been drawn with existing SRAM cell structures,the conventional 6T,PP, P4 and P3 cells.At the supply voltage,V_（DD） = 0.8 V,a reduction of 98%,99%,92%and 94%is observed in the gate leakage current in comparison with the 6T,PP,P4 and P3 SRAM cells,respectively,while at V_（DD） = 0.7 V,it is 97%,98%,87%and 84%.A significant reduction is also observed in the overall standby leakage power by 56%〉, the active write power by 44%and the active read power by 99%,compared with the conventional 6T SRAM cell at V_（DD）= 0.8 V,with no loss in cell stability and performance with a small area penalty.The simulation environment used for this work is 45 nm deep sub-micron complementary metal oxide semiconductor（CMOS） technology,t_（ox） = 2.4 nm,K_（thn） = 0.22 V,K_（thp） = 0.224 V,V_（DD） = 0.7 V and 0.8 V,at T = 300 K.