Recent advancements in continuously scalable conversion-ratio switched-capacitor converter

Switched-capacitor(SC)DC-DC converter[1]is an impor-tant alternative to inductive DC-DC converter,in terms of removing the bulky power inductor.Hence,it is widely used in low-profile,low-power applications,such as the internet of things(IoT)sensor nodes and energy harvesting[2].Mean-while,considering that capacitor has a much higher energy density than inductor,high-power applications.

Favorable basic cells for hybrid DC–DC converters

With the surging demands for extremely high current at sub-1 V supply voltage level in high performance computing and autonomous driving,high density power delivery becomes one of the critical limiting factors for system integration.48 V power bus system is emerging for these high current applications to reduce the IR losses on the power delivery networks.Thus,there is a wide voltage gap between the power bus and the digital supply rails at the point-of-load(PoL),calling for novel power conversion topologies and system architectures.Although the performances of the integrated power circuits heavily depend on both the quality factor of passive components and the figure-of-merit(FoM)of active devices,a smart circuit designer should also find an optimum way to guide the currents and to deliver the power.

Properties of Paths in ROBDD and Its Application to Signal Probability Calculations

The properties of the paths in an ROBDD representation of a Boolean function are presented and proved in the present paper, and the applications of ROBDD in calculating signal probability are also discussed. By this method, the troublesome calculation of the correlation among the nodes, which is caused by the re-convergent fan-out in digital system, can be avoided and power estimation can be faster than simulation-based method in [1].

The design of adaptive sigma-delta A/D converter

The signal to noise vatio (SNR) of conventional sigma delta analog to digital converter (ΣΔADC) reduces with input signal strength. The existing concept of adaptive quantization is applied to the design of ΣΔADC to improve SNR with high dynamic range. An adaptive algorithm and its circuit implementation is proposed. Because of the error due to the circuit implementation,an error self-calibration circuit is also designed. Simulation results indicate that SNR can be nearly independent of the signal strength.

A comparative study of digital low dropout regulators

Granular power management in a power-efficient system on a chip(SoC)requires multiple integrated voltage regulators with a small area,process scalability,and low supply voltage.Conventional on-chip analog low-dropout regulators(ALDOs)can hardly meet these requirements,while digital LDOs(DLDOs)are good alternatives.However,the conventional DLDO,with synchronous control,has inherently slow transient response limited by the power-speed trade-off.Meanwhile,it has a poor power supply rejection(PSR),because the fully turned-on power switches in DLDO are vulnerable to power supply ripples.In this comparative study on DLDOs,first,we compare the pros and cons between ALDO and DLDO in general.Then,we summarize the recent DLDO advanced techniques for fast transient response and PSR enhancement.Finally,we discuss the design trends and possible directions of DLDO.

Ring-VCO-based phase-locked loops for clock generation–design considerations and state-of-the-art

This article overviews the design considerations and state-of-the-art of the ring voltage-controlled oscillator(VCO)-based phase-locked loops(PLLs)for clock generation in different applications.Partic-ularly,the objective of the current work is to evaluate the required PLL performance among the fundamental metrics of power,jitter and area.An in-depth treatment of the mainstream PLL architectures and the associated design techniques enables them to be compared analyt-ically and benchmarked with respect to their figure-of-merit(FoM).The paper also summarizes the key concerns on the selection of dif-ferent circuit techniques to optimize the clock performance under dif-ferent scenarios.

A digital microfluidic system with 3D microstructures for single-cell culture

Despite the precise controllability of droplet samples in digital microfluidic(DMF)systems,their capability in isolating single cells for long-time culture is still limited:typically,only a few cells can be captured on an electrode.Although fabricating small-sized hydrophilic micropatches on an electrode aids single-cell capture,the actuation voltage for droplet transportation has to be significantly raised,resulting in a shorter lifetime for the DMF chip and a larger risk of damaging the cells.In this work,a DMF system with 3D microstructures engineered on-chip is proposed to form semi-closed micro-wells for efficient single-cell isolation and long-time culture.Our optimum results showed that approximately 20%of the micro-wells over a 30×30 array were occupied by isolated single cells.In addition,low-evaporation-temperature oil and surfactant aided the system in achieving a low droplet actuation voltage of 36V,which was 4 times lower than the typical 150 V,minimizing the potential damage to the cells in the droplets and to the DMF chip.To exemplify the technological advances,drug sensitivity tests were run in our DMF system to investigate the cell response of breast cancer cells(MDA-MB-231)and breast normal cells(MCF-10A)to a widely used chemotherapeutic drug,Cisplatin(Cis).The results on-chip were consistent with those screened in conventional 96-well plates.This novel,simple and robust single-cell trapping method has great potential in biological research at the single cell level.

Variables Bounding Based Retiming Algorithm

Retiming is a technique for optimizing sequential circuits. In this paper, wediscuss this problem and propose an improved retiming algorithm based on variables bounding.Through the computation of the lower and upper bounds on variables, the algorithm can signi-ficantly reduce the number of constraints and speed up the execution of retiming. Furthermore,the elements of matrixes D and W are computed in a demand-driven way, which can reducethe capacity of memory. It is shown through the experimental results on ISCAS89 benchmarksthat our algorithm is very effective for large-scale sequential circuits.