Mode decision based on rate-distortion optimization algorithm brings high compression efficiency to H.264/AVC. However, heavy computation load is also added to the encoder at the same time. In order to reduce the comp...Mode decision based on rate-distortion optimization algorithm brings high compression efficiency to H.264/AVC. However, heavy computation load is also added to the encoder at the same time. In order to reduce the computation burden of mode decision, this paper presented a fast mode decision method based on mode information of the previously coded frame. Moreover, all coding modes were activated when scene change occurs and a scheme to detect scene change was proposed. The simulation results show that compared to the original encoder, the proposed method achieves a reduction of over 38% encoding time and keeps almost the same PSNR and bitrate for a wide range of quantization parameter.展开更多
In this manuscript we analyze a unique approach to improve the performance of the bipolar charge plasma transistor(BCPT) by introducing a strained Si/SiGe1-x layer as the active device region. For charge plasma realiz...In this manuscript we analyze a unique approach to improve the performance of the bipolar charge plasma transistor(BCPT) by introducing a strained Si/SiGe1-x layer as the active device region. For charge plasma realization different metal work-function electrodes are used to induce n+ and p+ regions on undoped strained silicon-on-insulator(sSOI or SiGe) to realize emitter, base, and collector regions of the BCPT. Here,by using a calibrated 2-D TCAD simulation the impact of a Si mole fraction x(in SiGe) on device performance metrics is investigated. The analysis demonstrates the band gap lowering with decreasing Si content or effective strain on the Si layer, and its subsequent advantages. This work reports a significant improvement in current gain, cutoff frequency, and lower collector breakdown voltage(BVCEO) for the proposed structure over the conventional device. The effect of varying temperature on the strained Si layer and its implications on the device performance is also investigated. The analysis demonstrates a fair device-level understanding and exhibits the immense potential of the SiGematerial as the device layer. In addition to this, using extensive 2-D mixed-mode TCAD simulation, a considerable improvement in switching transient times are also observed compared to its conventional counterpart.展开更多
The advent of the memristor breaks the scaling limitations of MOS technology and prevails over emerging semiconductor devices. In this paper, various memristor models including behaviour, spice, and experimental are i...The advent of the memristor breaks the scaling limitations of MOS technology and prevails over emerging semiconductor devices. In this paper, various memristor models including behaviour, spice, and experimental are investigated and compared with the memristor＇s characteristic equations and fingerprints. It has brought to light that most memristor models need a window function to resolve boundary conditions. Various challenges of availed window functions are discussed with matlab＇s simulated results. Biolek＇s window is a most acceptable window function for the memristor, since it limits boundaries growth as well as sticking of states at boundaries. Simmons tunnel model of a memristor is the most accepted model of a memristor till now. The memristor is exploited very frequently in memory designing and became a prominent candidate for futuristic memories. Here, several memory structures utilizing the memristor are discussed. It is seen that a memristor-transistor hybrid memory cell has fast read/write and low power operations. Whereas,a 1 T1 R structure provides very simple,nanoscale,and non-volatile memory that has capabilities to replace conventional Flash memories. Moreover, the memristor is frequently used in SRAM cell structures to make them have non-volatile memory. This paper contributes various aspects and recent developments in memristor based circuits, which can enhance the ongoing requirements of modern designing criterion.展开更多
Nowadays FinFET devices have replaced the MOS devices almost in all complex integrated circuits of electronic gadgets like computer peripherals, tablets, and smartphones in portable electronics. The scaling of FinFET ...Nowadays FinFET devices have replaced the MOS devices almost in all complex integrated circuits of electronic gadgets like computer peripherals, tablets, and smartphones in portable electronics. The scaling of FinFET is ongoing and the analog/RF performance is most affected by increased SCEs(short channel effects) in sub22 nm technology nodes. This paper explores the analog/RF performance study and analysis of high performance device-D2(conventional Hf02 spacer SOI FinFET) and device-D3(source/drain extended Hf02 spacer SOI FinFET) over the device-D1(conventional Si3 N4 spacer SOI FinFET) at 20 nm technology node through the 3-D(dimensional) simulation process. The major performance parameters like I(ON current), I(OFF current), gm(transconductance), gd(output conductance), A(intrinsic gain), SS(sub-threshold slope), TGF = g/I(trans-conductance generation factor), VEA(early voltage), GTFP(gain trans-conductance frequency product), TFP(tansconductance frequency product), GFP(gain frequency product), and f(cut-off frequency) are studied for evaluating the analog/RF performance of different flavored SOI FinFET structures. For analog performance evaluation,device-D3 and D2 give better results in terms of gm, ID(drain current) and SS parameters, and for RF performance evaluation device-D1 is better in terms of f, GTFP, TFP, and GFP parameters both at low and high values of V=0.05 V and V=0.7 V respectively.展开更多
Continued scaling of CMOS technology to achieve high performance and low power consumption of semiconductor devices in the complex integrated circuits faces the degradation in terms of electrostatic integrity, short c...Continued scaling of CMOS technology to achieve high performance and low power consumption of semiconductor devices in the complex integrated circuits faces the degradation in terms of electrostatic integrity, short channel effects （SCEs）, leakage currents, device variability and reliability etc. Nowadays, multigate structure has become the promising candidate to overcome these problems. SO1 FinFET is one of the best multigate structures that has gained importance in all electronic design automation （EDA） industries due to its improved short channel effects （SCEs）, because of its more effective gate-controlling capabilities. In this paper, our aim is to ex- plore the sensitivity of underlap spacer region variation on the performance of SOI FinFET at 20 nm channel length. Electric field modulation is analyzed with spacer length variation and electrostatic performance is evalu- ated in terms of performance parameter like electron mobility, electric field, electric potential, sub-threshold slope （SS）, ON current （Ion）, OFF current （/off） and Ion/loll ratio. The potential benefits of SOl FinFET at drain-to-source voltage, liDS = 0.05 V and VDS = 0.7 V towards analog and RF design is also evaluated in terms of intrinsic gain （Av）, output conductance （go）, trans-conductance （gin）, gate capacitance （Cgg）, and cut-off frequency OCT = gm/2πCgg） with spacer region variations.展开更多
基金The National High Technology Research andDevelopment Program of China (863 Pro-gram) (No2002AA1Z1190)
文摘Mode decision based on rate-distortion optimization algorithm brings high compression efficiency to H.264/AVC. However, heavy computation load is also added to the encoder at the same time. In order to reduce the computation burden of mode decision, this paper presented a fast mode decision method based on mode information of the previously coded frame. Moreover, all coding modes were activated when scene change occurs and a scheme to detect scene change was proposed. The simulation results show that compared to the original encoder, the proposed method achieves a reduction of over 38% encoding time and keeps almost the same PSNR and bitrate for a wide range of quantization parameter.
文摘In this manuscript we analyze a unique approach to improve the performance of the bipolar charge plasma transistor(BCPT) by introducing a strained Si/SiGe1-x layer as the active device region. For charge plasma realization different metal work-function electrodes are used to induce n+ and p+ regions on undoped strained silicon-on-insulator(sSOI or SiGe) to realize emitter, base, and collector regions of the BCPT. Here,by using a calibrated 2-D TCAD simulation the impact of a Si mole fraction x(in SiGe) on device performance metrics is investigated. The analysis demonstrates the band gap lowering with decreasing Si content or effective strain on the Si layer, and its subsequent advantages. This work reports a significant improvement in current gain, cutoff frequency, and lower collector breakdown voltage(BVCEO) for the proposed structure over the conventional device. The effect of varying temperature on the strained Si layer and its implications on the device performance is also investigated. The analysis demonstrates a fair device-level understanding and exhibits the immense potential of the SiGematerial as the device layer. In addition to this, using extensive 2-D mixed-mode TCAD simulation, a considerable improvement in switching transient times are also observed compared to its conventional counterpart.
文摘The advent of the memristor breaks the scaling limitations of MOS technology and prevails over emerging semiconductor devices. In this paper, various memristor models including behaviour, spice, and experimental are investigated and compared with the memristor＇s characteristic equations and fingerprints. It has brought to light that most memristor models need a window function to resolve boundary conditions. Various challenges of availed window functions are discussed with matlab＇s simulated results. Biolek＇s window is a most acceptable window function for the memristor, since it limits boundaries growth as well as sticking of states at boundaries. Simmons tunnel model of a memristor is the most accepted model of a memristor till now. The memristor is exploited very frequently in memory designing and became a prominent candidate for futuristic memories. Here, several memory structures utilizing the memristor are discussed. It is seen that a memristor-transistor hybrid memory cell has fast read/write and low power operations. Whereas,a 1 T1 R structure provides very simple,nanoscale,and non-volatile memory that has capabilities to replace conventional Flash memories. Moreover, the memristor is frequently used in SRAM cell structures to make them have non-volatile memory. This paper contributes various aspects and recent developments in memristor based circuits, which can enhance the ongoing requirements of modern designing criterion.
文摘Nowadays FinFET devices have replaced the MOS devices almost in all complex integrated circuits of electronic gadgets like computer peripherals, tablets, and smartphones in portable electronics. The scaling of FinFET is ongoing and the analog/RF performance is most affected by increased SCEs(short channel effects) in sub22 nm technology nodes. This paper explores the analog/RF performance study and analysis of high performance device-D2(conventional Hf02 spacer SOI FinFET) and device-D3(source/drain extended Hf02 spacer SOI FinFET) over the device-D1(conventional Si3 N4 spacer SOI FinFET) at 20 nm technology node through the 3-D(dimensional) simulation process. The major performance parameters like I(ON current), I(OFF current), gm(transconductance), gd(output conductance), A(intrinsic gain), SS(sub-threshold slope), TGF = g/I(trans-conductance generation factor), VEA(early voltage), GTFP(gain trans-conductance frequency product), TFP(tansconductance frequency product), GFP(gain frequency product), and f(cut-off frequency) are studied for evaluating the analog/RF performance of different flavored SOI FinFET structures. For analog performance evaluation,device-D3 and D2 give better results in terms of gm, ID(drain current) and SS parameters, and for RF performance evaluation device-D1 is better in terms of f, GTFP, TFP, and GFP parameters both at low and high values of V=0.05 V and V=0.7 V respectively.
文摘Continued scaling of CMOS technology to achieve high performance and low power consumption of semiconductor devices in the complex integrated circuits faces the degradation in terms of electrostatic integrity, short channel effects （SCEs）, leakage currents, device variability and reliability etc. Nowadays, multigate structure has become the promising candidate to overcome these problems. SO1 FinFET is one of the best multigate structures that has gained importance in all electronic design automation （EDA） industries due to its improved short channel effects （SCEs）, because of its more effective gate-controlling capabilities. In this paper, our aim is to ex- plore the sensitivity of underlap spacer region variation on the performance of SOI FinFET at 20 nm channel length. Electric field modulation is analyzed with spacer length variation and electrostatic performance is evalu- ated in terms of performance parameter like electron mobility, electric field, electric potential, sub-threshold slope （SS）, ON current （Ion）, OFF current （/off） and Ion/loll ratio. The potential benefits of SOl FinFET at drain-to-source voltage, liDS = 0.05 V and VDS = 0.7 V towards analog and RF design is also evaluated in terms of intrinsic gain （Av）, output conductance （go）, trans-conductance （gin）, gate capacitance （Cgg）, and cut-off frequency OCT = gm/2πCgg） with spacer region variations.
