Nanowire devices with back gate are fabricated in a heavy doped ultra thin SOI layer by electron beam lithography. Regular and periodic Coulomb oscillations with single dot behavior are observed in an appropriate back...Nanowire devices with back gate are fabricated in a heavy doped ultra thin SOI layer by electron beam lithography. Regular and periodic Coulomb oscillations with single dot behavior are observed in an appropriate back gate voltage range. The oscillation period can be determined by the back gate capacitance. The role of the back gate can control the electrical characteristics from the multi-dot junction regimes to the single dot junction regimes. These Coulomb oscillations due to single-electron tunneling are not smeared out by thermal vibration energy when the temperature is less than 40 K.展开更多
A nonvolatile memory device with nitrided Si nanocrystals embedded in a floating gate was fabricated. The uniform Si nanocrystals with high density （3× 10^11 cm^-2 ） were deposited on ultra-thin tunnel oxide la...A nonvolatile memory device with nitrided Si nanocrystals embedded in a floating gate was fabricated. The uniform Si nanocrystals with high density （3× 10^11 cm^-2 ） were deposited on ultra-thin tunnel oxide layer （- 3 nm） and followed by a nitridation treatment in ammonia to form a thin silicon nitride layer on the surface of nanocrystals. A memory window of 2.4 V was obtained and it would be larger than 1.3 V after ten years from the extrapolated retention data. The results can be explained by the nitrogen passivation of the surface traps of Si nanoerystals, which slows the charge loss rate.展开更多
A carrier stored trench-gate bipolar transistor（CSTBT） with a p-floating layer（PF-CSTBT） is proposed. Due to the p-floating layer,the thick and highly doped carrier stored layer can be induced,and the conductivity...A carrier stored trench-gate bipolar transistor（CSTBT） with a p-floating layer（PF-CSTBT） is proposed. Due to the p-floating layer,the thick and highly doped carrier stored layer can be induced,and the conductivity modulation effect will be enhanced near the emitter.The accumulation resistance and the spreading resistance are reduced.The on-state loss will be much lower than in a conventional CSTBT.With the p-floating layer,the distribution of electric fields of the conventional IGBT is reformed,and the breakdown voltage is remarkably improved.The simulation results have shown that the forward voltage drop（VCE-on）） of the novel structure is reduced by 20%and 17%respectively, compared with the conventional trench IGBT（TIGBT） and CSTBT under the same conditions.Moreover,an increment of more than 100 V of the breakdown voltage is achieved without sacrificing the SCSOA（short circuit safety operation area） compared with the conventional TIGBT.展开更多
基金Supported by the National Basic Research Program of China under Grant No 2006CB932202, and the National Natural Science Foundation of China under Grant Nos 60721063 and 10974091.
文摘Nanowire devices with back gate are fabricated in a heavy doped ultra thin SOI layer by electron beam lithography. Regular and periodic Coulomb oscillations with single dot behavior are observed in an appropriate back gate voltage range. The oscillation period can be determined by the back gate capacitance. The role of the back gate can control the electrical characteristics from the multi-dot junction regimes to the single dot junction regimes. These Coulomb oscillations due to single-electron tunneling are not smeared out by thermal vibration energy when the temperature is less than 40 K.
基金Supported by the National Basic Research Program of China under Grant No 2006CB932202, and the National Natural Science Foundation of China under Grant Nos 60721063 and 10974091.
文摘A nonvolatile memory device with nitrided Si nanocrystals embedded in a floating gate was fabricated. The uniform Si nanocrystals with high density （3× 10^11 cm^-2 ） were deposited on ultra-thin tunnel oxide layer （- 3 nm） and followed by a nitridation treatment in ammonia to form a thin silicon nitride layer on the surface of nanocrystals. A memory window of 2.4 V was obtained and it would be larger than 1.3 V after ten years from the extrapolated retention data. The results can be explained by the nitrogen passivation of the surface traps of Si nanoerystals, which slows the charge loss rate.
文摘A carrier stored trench-gate bipolar transistor（CSTBT） with a p-floating layer（PF-CSTBT） is proposed. Due to the p-floating layer,the thick and highly doped carrier stored layer can be induced,and the conductivity modulation effect will be enhanced near the emitter.The accumulation resistance and the spreading resistance are reduced.The on-state loss will be much lower than in a conventional CSTBT.With the p-floating layer,the distribution of electric fields of the conventional IGBT is reformed,and the breakdown voltage is remarkably improved.The simulation results have shown that the forward voltage drop（VCE-on）） of the novel structure is reduced by 20%and 17%respectively, compared with the conventional trench IGBT（TIGBT） and CSTBT under the same conditions.Moreover,an increment of more than 100 V of the breakdown voltage is achieved without sacrificing the SCSOA（short circuit safety operation area） compared with the conventional TIGBT.
