Metrology Challenges in 3D NAND Flash Technical Development and Manufacturing

3D NAND technical development and manufacturing face many challenges to scale down their devices,and metrology stands out as much more difficult at each turn.Unlike planar NAND,3D NAND has a three-dimensional vertical structure with high-aspect ratio.Obviously top-down images is not enough for process control,instead inner structure control becomes much more important than before,e.g.channel hole profiles.Besides,multi-layers,special materials and YMTC unique X-Tacking technology also bring other metrology challenges:high wafer bow,stress induced overlay,opaque film measurement.Technical development can adopt some destructive methodology(TEM,etch-back SEM),while manufacturing can only use nondestructive method.These drive some new metrology development,including X-Ray,mass measure and Mid-IR spectroscopy.As 3D NAND suppliers move to>150 layers devices,the existing metrology tools will be pushed to the limits.Still,the metrology must innovate.

Effect of the relative phase between pre-existing 2/1 and 3/1 magnetic islands on the suppression of runaway electrons on J-TEXT

In the experiments of actively triggering plasma disruption by massive gas injection, the externally applied resonant magnetic perturbation has been used to mitigate the hazard of runaway electron(RE). Motivated by the experiment of multimode coupling to suppress REs on J-TEXT, some typical simulation cases with non-ideal MHD with rotation-open discussion(NIMROD) code are carried out to explore the influential mechanism of different relative phases between m/n =2/1 and m/n = 3/1 magnetic islands on the confinement of REs. Results show that the RE confinement is drastically affected by the relative phase between 2/1 and 3/1 magnetic islands. When the O point phase of 2/1 and 3/1 magnetic islands is toroidal 330°, REs can be effectively lost. The fitting curve of the remaining ratio of REs vs. the relative toroidal phase is predicted to approximate a sine-like function dependence. Further studies indicate that the phase difference between coexisting 2/1 and 3/1 islands can affect the radial transport of impurities. The loss of runaway electrons is closely related to the deposition effect of impurity. The impurity is easier to spread into the core region with smaller poloidal phase difference between the radial velocity of impurity and the impurity quantity of Ar.

Novel Pattern-Centric Solution for Xtacking^TM AFM Metrology

3D NAND(three-dimensional NAND type)has rapidly become the standard technology for enterprise flash memories,and is also gaining widespread use in other applications.Continued manufacturing process improvements are essential in delivering memory devices with higher I/O performance,higher bit density,and at lower cost.Current 3D NAND technology involves process steps that form array and peripheral CMOS(Complementary Metal-Oxide-Semiconductor)regions side-by-side,resulting in waste of silicon real estate and film stress compromises,and limits the paths of making advanced 3D NAND devices.An innovative architecture was invented to overcome these challenges by connecting two wafers electrically through metal VIAs(Vertical Interconnect Access)[1].Highly accurate and efficient metrology is required to monitor VIA interface due to increased process complexity and precision requirements.With the advanced processing of AFM(Atomic Force Microscopy)images,highly accurate and precise measurements have been achieved.An inline pattern-centric metrology solution that is designed for high volume mass production of high-performance 3D NAND is presented in this paper.

White Light Interference Solution for Novel 3D NAND VIA Dishing Metrology

In traditional 3D NAND design,peripheral circuit accounts for 20-30%of the chip realestate,which reduces the memory density of flash memory.As 3D NAND technology stacks to 128 layers or higher,peripheral circuits may account for more than 50%of the overall chip area.On the contrast,the Xtacking^TM technology arranges array and logic parts on two different wafers,and connects the memory arrays to the logic circuit by metal VIAs(Vertical Interconnect Accesses)to achieve unprecedented high storage density as well as DRAM level I/O speed.As a consequence,it becomes increasingly significant to monitor metal VIAs depth before wafer bonding process as to ensure reliability of array-logic connections.Currently,AFM(Atom Force Microscopy)is the main stream method of VIA depth monitoring.Apparently,AFM wins the battle of precision,however the low throughput limited its usage in mass production.In order to accomplish the requirement of VLSI production,a WLI(White Light Interference)metrology is revisited and a novel WLI method was developed to monitor VIAs depth.Basically there are two major limitations that keep WLI tools from wider use,transparent film impact and diffraction limitation.In this work,the engineering solutions are illustrated and inline dishing measurement is achieved with high accuracy and precision.

Machine Learning based Optical Proximity Correction Techniques

The shrinking of the size of the advanced technological nodes brings up new challenges to the semiconductor manufacturing community.The optical proximity correction(OPC)is invented to reduce the errors of the lithographic process.The conventional OPC techniques rely on the empirical models and optimization methods of iterative type.Both the accuracy and computing speed of the existing OPC techniques need to be improved to fulfill the stringent requirement of the research and design for latest technological nodes.The emergence of machine learning technologies inspires novel OPC algorithms.More accurate forward simulation of the lithographic process and single turn optimization methods are enabled by the machine learning based OPC techniques.We discuss the latest progress made by the OPC community in the process simulation and optimization based on machine learning techniques.

Mechanical system and dynamic control in photolithography for nanoscale fabrication: A critical review

As one of the most advanced and precise equipment in the world,a photo-lithography scanner is able to fabricate nanometer‐scale devices on a chip.To realize such a small dimension,the optical system is the fundamental,but the me-chanical system often becomes the bottleneck.In the photolithography,the ex-posure is a dynamic process.The accuracy and precision of the movement are determined by the mechanical system,which is even more difficult to control compared with the optical system.In the mechanical system,there are four crucial components:the reticle and wafer stages,the linear motor,the metrology system,and the control system.They work together to secure the reticle and substrate locating at the correct position,which determines the overlay and alignment per-formance in the lithography.In this paper,the principles of these components are reviewed,and the development history of the mechanical system is introduced.