Verilog HDL modeling and design of 10Gb/s SerDes full rate CDR in 65nm CMOS

Phase locked loop(PLL) is a typical analog-digital mixed signal circuit and a method of conducting a top level system verification including PLL with standard digital simulator becomes especially significant.The behavioral level model(BLM) of the PLL in Verilog-HDL for pure digital simulator is innovated in this paper,and the design of PLL based clock and data recovery(CDR)circuit aided with jitter attenuation PLL for SerDes application is also presented.The CDR employs a dual-loop architecture where a frequency-locked loop acts as an acquisition aid to the phase-locked loop.To simultaneously meet jitter tolerance and jitter transfer specifications defined in G.8251 of optical transport network(ITU-T OTN),an additional jitter attenuation PLL is used.Simulation results show that the peak-to-peak jitter of the recovered clock and data is 5.17 ps and 2.3ps respectively.The core of the whole chip consumes 72 mA current from a 1.0V supply.

A Detailed Thermal Resistance Network Analysis of FCBGA Package

Using thermal models to describe the heat dissipation process of FCBGA is a significant topic in the field of packaging.However,the thermal resistance model considering the structure of each part of the chip is still ambiguous and rare,but it is quite desirable in engineering.In this work,we propose a detailed thermal resistance network model,and describe it by using thermal conduction resistance and thermal spreading resistance.For a striking FCBGA case,we calculated the thermal resistance of each part of the structure according to the temperature field simulated by COMSOL.The thermal resistance network can be used to predict the temperatures in the chip under different conditions.For example,when the power changes by 40%,the relative error of junction temperature prediction is only 0.24%.The function of the detailed thermal resistance network in evaluating the optimization space and determining the optimization direction is clarified.This work illustrates a potential thermal resistance analysis method for electronic devices such as FCBGA.

Jitter analysis and modeling of a 10 Gbit/s SerDes CDR and jitter attenuation PLL

Jitter analysis and a linear model is proposed in this paper which predicts the characteristics of serial-deserial （SerDes） clock and data recovery circuit, and the characteristics include jitter transfer, jitter tolerance and jitter generation are particularly analyzed. The simulation results of the clock data recovery （CDR） model show that the jitter specifications exceed the mask of ITU-T optical transport network （OTN） G.8251 recommendations. The whole systems are validated by 9.95-11.5 Gbit/s CDR and the jitter attenuation phase locked loops （PLL） circuits using TSMC 65 nm CMOS technology.