A new PMSM speed modulation system with sliding mode based on active-disturbance-rejection control

A sliding mode and active disturbance rejection control(SM-ADRC)was employed to regulate the speed of a permanent magnet synchronous motor(PMSM).The major advantages of the proposed control scheme are that it can maintain the original features of ADRC and make the parameters of ADRC transition smoothly.The proposed control scheme also ensures speed control accuracy and improves the robustness and anti-load disturbance ability of the system.Moreover,through the analysis of a d-axis current output equation,a novel current-loop SM-ADRC is presented to improve the system’s dynamic performance and inner ability of anti-load disturbance.Results of a simulation and experiments show that the improved sliding-mode ADRC system has the advantages of fast response,small overshoot,small steady-state error,wide speed range and high control accuracy.It shows that the system has strong anti-interference ability to reduce the influence of variations in rotational inertia,load and internal parameters.

Annealing temperature influence on the degree of inhomogeneity of the Schottky barrier in Ti/4H–SiC contacts

Tung＇s model was used to analyze anomalies observed in Ti/Si C Schottky contacts. The degree of the inhomogeneous Schottky barrier after annealing at different temperatures is characterized by the ‘T0anomaly＇ and the difference（△Φ）between the uniformly high barrier height（Φ0B） and the effective barrier height（Φeff B）. Those two parameters of Ti Schottky contacts on 4H–Si C were deduced from I–V measurements in the temperature range of 298 K–503 K. The increase in Schottky barrier（SB） height（ΦB） and decrease in the ideality factor（n） with an increase measurement temperature indicate the presence of an inhomogeneous SB. The degree of inhomogeneity of the Schottky barrier depends on the annealing temperature, and it is at its lowest for 500-°C thermal treatment. The degree of inhomogeneity of the SB could reveal effects of thermal treatments on Schottky contacts in other aspects.

Numerical and experimental study of the mesa configuration in high-voltage 4H–SiC PiN rectifiers

The effect of the mesa configuration on the reverse breakdown characteristic of a SiC PiN rectifier for high-voltage applications is analyzed in this study.Three geometrical parameters,i.e.,mesa height,mesa angle and mesa bottom corner,are investigated by numerical simulation.The simulation results show that a deep mesa height,a small mesa angle and a smooth mesa bottom（without sub-trench） could contribute to a high breakdown voltage due to a smooth and uniform surface electric field distribution.Moreover,an optimized mesa structure without sub-trench（mesa height of 2.2 μm and mesa angle of 20°） is experimentally demonstrated.A maximum reverse blocking voltage of 4 kV and a forward voltage drop of 3.7 V at 100 A/cm^2 are obtained from the fabricated diode with a 30-μm thick N^- epi-layer,corresponding to 85% of the ideal parallel-plane value.The blocking characteristic as a function of the JTE dose is also discussed for the PiN rectifiers with and without interface charge.

Energy-band alignment of atomic layer deposited(HfO_2)_x(Al_2O_3)_(1-x) gate dielectrics on 4H-SiC

We study a series of（HfO2）x（Al2O3）1-x /4H-SiC MOS capacitors. It is shown that the conduction band offset of HfO2 is 0.5 e V and the conduction band offset of Hf AlO is 1.11–1.72 e V. The conduction band offsets of（Hf O2）x（Al2O3）1-x are increased with the increase of the Al composition, and the（HfO2）x（Al2O3）1-x offer acceptable barrier heights（〉 1 e V）for both electrons and holes. With a higher conduction band offset,（Hf O2）x（Al2O3）1-x/4H-SiC MOS capacitors result in a ～ 3 orders of magnitude lower gate leakage current at an effective electric field of 15 MV/cm and roughly the same effective breakdown field of ～ 25 MV/cm compared to HfO2. Considering the tradeoff among the band gap, the band offset, and the dielectric constant, we conclude that the optimum Al2O3 concentration is about 30% for an alternative gate dielectric in 4H-Si C power MOS-based transistors.

Controllable ion exchange synthesis of Ir/Carbon catalyst

In this paper,a carbon based iridium (Ir) catalyst was prepared by an ion exchange procedure using H2IrCl6 as precursor and a strong basic anion exchange resin as substrate. The Ir/Carbon sample was obtained by carbonizing the precursor. Effects of carbonization parameters such as temperature and time on size and dispersion of iridium crystallite were studied. Samples were prepared at 400 oC and 500 oC to investigate the effect of carbonization temperature. The SEM image of the Ir/Carbon composite shows a hard particle of 0. 2 - 0. 4 mm in diameter,which maintains a spherical shape. The TEM images of the catalyst show that no obvious effects of carbonization temperature or time are observed on the iridium particle size. Calcinated Ir nanoparticles prepared in ion exchange still keep their small particle-sized and narrow-sized distribution. The content of Ir supported on carbon can be well controlled simply by adjusting the relative ratio of Ir to carbon. Such a promising synthesis procedure is a versatile approach that can be extended to the fabrication of some carbon-supported metal catalysts or as a simple,rapid,and highly sensitive method.

Fabrication and Characterization of 1700 V 4H-SiC Vertical Double-Implanted Metal-Oxide-Semiconductor Field-Effect Transistors

The fabrication and characterization of 1700 V 7 A 4H-SiC vertical double-implanted metal-oxide-semiconductor field-effect transistors （VDMOSFETs） are reported. The drift layer is 17μm in thickness with 5 × 10^15 cm^-3 n-type doping, and the channel length is 1μm. The MOSFETs show a peak mobility of 17cm2/V.s and a typical threshold voltage of 3 V. The active area of 0.028cm2 delivers a forward drain current of 7A at Vcs = 22 V and VDS= 15 V. The specific on-resistance （Ron,sv） is 18mΩ.cm2 at VGS= 22 V and the blocking voltage is 1975 V （IDS 〈 lOOnA） at VGS = 0 V.

Influences of high-temperature annealing on atomic layer deposited Al_2O_3/4H-SiC

High-temperature annealing of the atomic layer deposition （ALD） of Al2O3 films on 4H-SiC in O 2 atmosphere is studied with temperature ranging from 800℃ to 1000℃. It is observed that the surface morphology of Al2O3 films annealed at 800℃ and 900℃ is pretty good, while the surface of the sample annealed at 1000℃ becomes bumpy. Grazing incidence X-ray diffraction （GIXRD） measurements demonstrate that the as-grown films are amorphous and begin to crystallize at 900℃. Furthermore, C–V measurements exhibit improved interface characterization after annealing, especially for samples annealed at 900℃ and 1000℃. It is indicated that high-temperature annealing in O2 atmosphere can improve the interface of Al2O3 /SiC and annealing at 900℃ would be an optimum condition for surface morphology, dielectric quality, and interface states.

Charge trapping behavior and its origin in Al_2O_3/SiC MIS system

Charge trapping behavior and its origin in Al2O3/SiC MOS structure are investigated by analyzing the capacitance–voltage(C–V) hysteresis and the chemical composition of the interface. The C–V hysteresis is measured as a function of oxide thickness series for an Al2O3/SiC MIS capacitor. The distribution of the trapped charges, extracted from the C–V curves, is found to mainly follow a sheet charge model rather than a bulk charge model. Therefore, the electron injection phenomenon is evaluated by using linear fitting. It is found that most of the trapped charges are not distributed exactly at the interface but are located in the bulk of the Al2O3 layers, especially close to the border. Furthermore, there is no detectable oxide interface layer in the x-ray photoelectron spectroscope(XPS) and transmission electron microscope(TEM)measurements. In addition, Rutherford back scattering(RBS) analysis shows that the width of the Al2O3/SiC interface is less than 1 nm. It could be concluded that the charge trapping sites in Al2O3/SiC structure might mainly originate from the border traps in Al2O3 film rather than the interface traps in the interfacial transition layer.

Characterization of the effects of nitrogen and hydrogen passivation on SiO2/4H-SiC interface by low temperature conductance measurements

We investigate the effects of NO annealing and forming gas （FG） annealing on the electrical properties of a SiO2/SiC interface by low-temperature conductance measurements. With nitrogen passivation, the density of interface states （DIT） is significantly reduced in the entire energy range, and the shift of flatband voltage, AVFB, is effectively suppressed to less than 0.4 V. However, very fast states are observed after NO annealing and the response frequencies are higher than 1 MHz at room temperature. After additional FG annealing, the DIT and AVFB are further reduced. The values of the DIT decrease to less than 1011 cm-2 eV- 1 for the energy range of Ec - ET 〉/0.4 eV. It is suggested that the fast states in shallow energy levels originated from the N atoms accumulating at the interface by NO annealing. Though FG annealing has a limited effect on these shallow traps, hydrogen can terminate the residual Si and C dangling bonds corresponding to traps at deep energy levels and improve the interface quality further. It is indicated that NO annealing in conjunction with FG annealing will be a better post-oxidation process method for high performance SiC MOSFETs.

Improved adhesion and interface ohmic contact on n-type 4H-SiC substrate by using Ni/Ti/Ni

The Ni/Ti/Ni multilayer ohmic contact properties on a 4H-SiC substrate and improved adhesion with the Ti/Au overlayer have been investigated. The best specific contact resistivity of 3.16 × 10^-5 Ω.cm^2 was obtained at 1050 ℃. Compared with Ni/SiC ohmic contact, the adhesion between Ni/Ti/Ni/SiC and the Ti/Au overlayer was greatly improved and the physical mechanism under this behavior was analyzed by using Raman spectroscopy and X-ray energy dispersive spectroscopy （EDS） measurement. It is shown that a Ti-carbide and Ni-silicide compound exist at the surface and there is no graphitic carbon at the surface of the Ni/Ti/Ni structure by Raman spectroscopy, while a large amount of graphitic carbon appears at the surface of the Ni/SiC structure, which results in its bad adhesion. Moreover, the interface of the Ni/Ti/Ni/SiC is improved compared to the interface of Ni/SiC.

Effect of post oxidation annealing in nitric oxide on interface properties of 4H-SiC/SiO_2 after high temperature oxidation

The interface properties of 4H-SiC metal oxide semiconductor （MOS） capacitors with post-oxidation annealing （POA） in nitric oxide （NO） ambient after high temperature （1300 ℃） oxidation have been investigated using capacitance-voltage （C V） measurements. The experimental results show that the interface states density （Dit） can be obviously decreased by the POA in NO ambient （NO-POA） and further reduced with increasing POA temperature and time. In the meantime significant reduction of the interface states density and oxidation time can be achieved at the higher thermal oxidation temperature, which results in the better oxide MOS characteristics and lower production costs. The dependence of Dit on POA temperature and time has been also discussed in detail.

Characteristics and analysis of 4H-SiC PiN diodes with a carbon-implanted drift layer

The characteristics of 4H-SiC PiN diodes with a carbon-implanted drift layer was investigated and the reason of characteristics improvement was analyzed. The forward voltage drops of the diodes with carbonimplanted drift layer were around 3.3 V, which is lower than that of devices without carbon implantation, the specific-on resistance was decreased from 9.35 to 4.38 mΩcm^2 at 100 A/cm^2, and the reverse leakage current was also decreased. The influence of carbon incorporation in the Si C crystalline grids was studied by using deep-level transient spectroscopy（DLTS）. The DLTS spectra revealed that the Z_（1/2） traps, which were regarded as the main lifetime limiting defects, were dramatically reduced. It is proposed that the reduction of Z_（1/2） traps can achieve longer carrier lifetime in the drift layer, which is beneficial to the performance of bipolar devices.